AMD Announces Genoa-X, Siena and Turin Server EPYC Processors

At the Financial Analysts Day 2022 reporting event this evening, AMD shared its plans for further development of the EPYC server processor. These products were already announced, as well as completely new, for segments that were not previously dominated by the company.

Most notable, at least in detail, was the official announcement of the fifth generation AMD EPYC, code-named Turin (EPYC 7005), which is expected to appear by the end of 2024. They will be based on the significantly redesigned Zen 5 architecture and will be manufactured using it. 3 and 4 nm mixed processing technology. Three types of crystals are promised: regular, with 3D V-Cache, and “Cloud” (Zen 5c), optimized to increase placement density. The important thing here is that in this way the continuity of generations will be maintained, which will definitely please the customers.

But in the near future we look forward to the release of AMD EPYC Genoa, which should happen in the fourth quarter of this year. This 5nm processor will have 96 Zen 4 cores, 12 DDR5 channels, PCIe 5.0 and CXL support. And now the possibility of expanding system memory using CXL is already clearly stated. The transition to a new technical process and a 1.5x increase in the number of cores led to an increase in performance up to + 75% (e.g. Java SPECjbb test).

Genoa will need a new SP5 socket (LGA6096). It will be ready to accept two more processor options. The first is the brand new Genoa-X, whose name is easy to guess that it is the same Genoa (up to 96 cores), equipped with the expanded 3D V-Cache L3 cache (1GB or more). Like Milan-X, it will target a specific class of workload that takes advantage of the increasing available cache. These are, for example, calculation functions and DBMS.

Genoa-X will appear in 2023. So it’s worth waiting for a special series from Bergamo. These processors, as promised earlier, will receive up to 128 cores (and 256 threads) compatible with the SP5 socket. They will be based on the 5nm Zen 4c core, somewhat reminiscent of Intel’s e-core. However, the command set for Zen 4c will be the same as Zen 4. AMD has not disclosed the details of the c-core device, but it can be assumed that they have redesigned the cache hierarchy. They are for hyperscalers who take care of not only performance but also resource density.

In 2023, the “small” EPYC will appear under the code name Siena. They are optimized for energy efficiency and offer up to 64 Zen 4 cores. Siena Edge focuses on computing and telecom. Details about them are also lacking. With built-in “smart” network controllers, we can see hybrids like Ice Lake-D.

All new products will require the use of the Zen 4 architecture (4 and 5 nm), which, in addition to the expected increase in functionality, will acquire new features. This includes support for the AVX-512 (probably not the most complete set) and new instructions for AI workloads that Intel has been showing for years. But most importantly, the Zen 4 will receive the fourth generation of the Infinity Architecture interconnect, which will allow you to connect more tightly to multiple chiplets and silicone layers (2.5D and 3D packaging).

And it paves the way for efficient packaging of multiple functional modules with support for chip-wide compatibility – AMD has reaffirmed its ability to integrate Xilinx FPGAs and third-party IP blocks. The new interconnect is compatible with CXL 2.0, which is important for working with memory, and future versions will support CXL 3.0 and UCIE. It was the fourth generation of Infinity that allowed AMD to build the first Instinct MI300 server APUs.

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